Unfortunately, due to the complexity and specialized nature of AVX-512, such optimizations are typically reserved for performance-critical applications and require expertise in low-level programming and processor microarchitecture.
Whomever wrote this article is just misleading everyone.
First of all, they did this for other kinds of similar instruction sets before, so this is nothing special. Second of all, they measure the speedup compared to a basic implementation that doesn’t use any optimizations.
They did the same in the past for AVX-2, which is 67x faster in the test where avx-512 got the 94x speed increase. So it’s not 94x faster now, it’s 1.4x faster than the previous iteration using the older AVX-2 instruction set. It’s barely twice as fast as the implementation using SSE3 (40x faster than the slow version), an instruction set from 20 years ago…
So yeah, it’s awesome that they did the same awesome work for AVX-512, but the 94x boost is just plain bullshit… it’s really sad that great work then gets worded in such a misleading way to form clickbait, rather than getting a proper informative article…
Even more ridiculous since a 1.4x performance increase is already incredible news for anyone who makes regular of this.
If someone found a software optimization that improved, say, blender performance by 1.4x people would be shouting praises from the rooftops.
Indeed, it’s a very nice boost, and great work, but this clickbait nonsense is just so stupid…
And i’m really bothered how it’s just parrotted everywhere… Doesn’t anybody wonder “94x faster is like… really a LOT… that can’t be true”
The only thing the article adds to the headline is that it’s not possible on new Intel chips. This article seems significantly better.
Relevant section:
Intel made waves when it disabled AVX-512 support at the firmware level on 12th-gen Core processors and later models, effectively removing the SIMD ISA from its consumer chips.
There is an issue, though: Intel disabled AVX-512 for its Core 12th, 13th, and 14th Generations of Core processors, leaving owners of these CPUs without them. On the other hand, AMD’s Ryzen 9000-series CPUs feature a fully-enabled AVX-512 FPU so the owners of these processors can take advantage of the FFmpeg achievement.
Intel can’t stop the L.
As for the claims and benchmarking, we need to see how much it actually improves. Because the 94x performance boost is compared to baseline when no AVX or SIMD is used (if I understand the blog post correctly). So I wonder how much the handwritten AVX-512 assembler code improves over an AVX-512 code written in C (or Rust maybe?). The exact hardware used to benchmark this is not disclosed either, unfortunately.
Someone else in the comments mentioned it is about 40% faster than the AVX-2 code and slightly more than twice as fast as the SSE3 code. That’s still a nice boost, but hopefully no one was relying on the radically slow unoptimized baseline.
As someone who has done some hand coding of AVX-512, I appreciate their willingness to take this on. Getting the input vectors setup correctly for the instructions can be a hassle, especially when the input dataset is not an even multiple of 64.
I worked in the media broadcasting, we had an internal lib to scale/convert whatever format in real time, and it went from basic operation, to SSE3, to AVX512, to CUDA, and yes crafting some functions/loops wit assembly can give an enormous boost.
